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EM MICROELECTRONIC - MARIN SA
H6006
Failsafe Watchdog
Description
The H6006 is a monolithic low power CMOS device combining a programmable digital timer and a series of voltage comparators on the same chip. The device is specially convenient for Watch-Dog functions such as microprocessor and supply voltage monitoring. The watchdog part is designed to be used in all applications where it is important that after the occurrence of a malfunction the microprocessor system is stopped to avoid further damage. The timeout warning signal ( TO ) can be used to try to reactivate the system before halting it. The voltage monitoring part provides double security by combining both unregulated voltage and regulated voltage monitoring simultaneously. The H6006 initializes the poweron reset after VIN reached VSH and VDD raises above 3.5 V. If VIN drops below VSL, the H6006 gives an advanced warning signal for register saving and if the voltage drops further below VRL, RES goes active. The H6006 functions at any supply voltage down to 1.5 V and is therefore particularly suited for start-up and shut-down control of microprocessor systems
Features
Failsafe watchdog function: timeout warning after 1st timeout period, reset after 2nd timeout period, reset remains active to avoid further failures Standard timeout period and power-on reset time (10 ms), externally programmable if required VIN monitoring with 3 standard or programmable trigger voltages for: power-on reset initialization, advanced power-fail warning ( SAVE ), reset at power-down ( RES ) VDD monitoring: power-on reset initialization enabled only if VDD 3.5 V Internal voltage reference Works down to 1.5 V supply voltage Push-pull or Open drain outputs Low current consumption Available for normal and extended temperature range SO8 package
Applications
Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems
Typical Operating Configuration
Pin Assignment
Voltage Regulator
5V
SO8
VIN VIN VDD TCL TO SAVE RES INT NMI RES I/O TCL RC VSS
VDD TO SAVE RES
H6006
Microprocessor
H6006
VSS
GND
Fig. 1
Fig. 2
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H6006
Absolute Maximum Ratings
Parameter Voltage VDD to VSS Voltage at any pin to VSS Voltage at any pin to VDD(except VIN) Voltage at VIN to VSS Current at any output Storage temperature Symbol Conditions VDD -0.3 to +8 V VMIN -0.3 +0.3 VMAX
VINMAX IMAX TSTO +15 V 10 mA -65... +150 C
Table 1
Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Symbol Min. Parameter Operating temperature Industrial TAI -40 Supply voltage VDD 1.5 Comparator input voltage Version A2, A3, VIN 0 B2,B3 Version B1 VIN 0 RC-oscillator programming (see Fig. 15) External capacitance C1 External resistance R1 10 Typ Max. Units
+85 5.5 VDD 12
Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
C V
V V
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component.
100
nF k
Table 2
Electrical Characteristics
VDD = 5.0 V, TA = -40 to +85 C, unless otherwise specified
Parameter VDD activation threshold VDD deactivation threshold Supply current Input VIN,, TCL Leakage current
Input current on pin VIN TCL input low level TCL input high level TO , RES . SAVE Outputs Leakage current
Symbol VON VOFF IDD
IIP IIN VIL VIH IOLK
Test Conditions TA = 25 C TA = 25 C RC open, TCL= 5 V, VIN = 0 V
VSS VIP VDD; TA = 85 C Version B1; VIN = 10 V
Min. 3
Typ.
VON - 1.5 50
Max. 3.5
140
Units V V A
0.005 100 2.4
1 180 0.8
A A V V
Versions A2, A3; VOUT = VDD Drive currents (all versions) IOL VOL = 0.4 V IOL VDD = 3.5 V; VOL = 0.4 V IOL VDD = 1.6 V; VOL = 0.4 V Drive currents IOH VOH = 4.0 V 1) (versions B1, B2, B3) IOH VDD = 3.5 V; VOH 2.8 V IOH VDD = 1.6 V; VOH = VDD-0.4 1) Versions: An = open drain outputs; Bn = push-pull outputs
3.2 2 80 3.2 2 80
0 .05 8
1
8
A mA mA A mA mA A
Table 3
VIN Surveillance Voltage thresholds at TA = 25 C Version1)
B1 A2, B2 A3, B3
1) 2)
Comparator Reference
VDD VDD Band-gap reference
Input Resistance RVIN
100k ~100M ~100M
Thresholds
9.00 8.00 7.00 2) 2.25 2.00 1.75 2.00 1.95 1.90
2)
Threshold Tolerance 5% 5% 10%
Ratio Tolerance 3)
+2% +2% +2%
Versions: An = open drain outputs; Bn = push-pull outputs at VDD = 5 V 3) Threshold ratio as VSH/VSL or VSL/VRL
Table 4
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H6006
Timing Characteristics
VDD = 5.0 V, TA = -40 C to +85 C, unless otherwise specified
Parameter Propagation delays TCL to output pins VIN to output pins Logic transition times on all output pins Timeout period
TTCL input pulse width Power-on reset debounce
Symbol
TDIDO TAIDO TTR TTO TTO TTCL TDB
Test Conditions
Min.
Typ.
250 4 30
Max.
500 10 100 16 20
Units
ns s ns ms ms ns ms
Table 5
Excluding debounce time TDB Load 10 k, 100 pF RC open, unshielded , TA =25 C RC open, unshielded (not tested) 6 4.5 150
10
TTO/32
Timing Waveforms Voltage Reaction: VDD Monitoring
VDD
VON VOFF
VIN monitoring enabled
Fig. 3
Voltage Reaction: VIN Monitoring
VIN VSH VSL VRL TTO 0 TDB TDB TTO Conditions: VDD > VON No timeout
SAVE RES Timer Start Power-on Reset Timer Stop Timer Start Power-on Reset
No Power-on Reset (as VIN > VRL)
Fig. 4
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H6006
Timer Reaction
Conditions: VIN > VRL after power-up sequence. TTCL
______
TCL TO
TTO TTO TTO
RES
Timer Reset TO Timeout RES Timeout Timer Reset Timer Reset Fig. 5
Combined Voltage and Timer Reaction
VSH VSL VRL VIN
TDB SAVE RES TO TCL
Power-on Reset
TTO TTO TTO TTO
TO Timeout
RES Timeout
Timer Reset
TO Timeout
Timer Stop
Fig. 6
Block Diagram
VDD
1 2
VIN
Band-Gap Reference
VSH
Save Control SAVE
VSL
Reset VRL Control RES
Version B1 A2, B2 A3, B3
TO TCL
Connections 1 and 3 1 2
Fig. 7
VSS RC
3
OSC
Timer
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H6006
Pin Description
Pin 1 2 3 4 5 6 7 8 Name VIN TCL RC VSS RES SAVE TO VDD Function Voltage monitoring input Timer clear input signal RC oscillator tuning input GND terminal Reset output Save output Timer output signal Positive supply voltage terminal
Table 6
Version B1: with internal voltage divider, resulting in thresholds for direct monitoring of the unregulated voltage without external components.
>9V Voltage Regulator 5V VIN VDD
H6006 B1
VSS any voltage Voltage Regulator 5V
Functional Description
Supply Lines The circuit is powered through the VDD and VSS pins. It monitors both its own VDD supply and a voltage applied to the VIN input. VDD Monitoring During power-up the VIN monitoring is disabled and RES and SAVE stay active low as long as VDD is below VON (3.5 V). As soon as VDD reaches the VON level, the state of the outputs depend on the watchdog timer and the volt-age at VIN relative to the thresholds (see Fig. 3 and 4). If the supply voltage VDD falls back below VOFF (1.5 V) the watchdog timer and the VIN monitoring are disabled and the outputs SAVE and RES are active low. The VDD line should be free of spikes. VIN Monitoring The analog voltage comparators compare the voltage applied to VIN (typically connected to the input of the voltage regulator) with the stabilized supply voltage VDD (versions B1, A2, B2) or with the bandgap voltage (versions A3, B3) (see Fig. 7). At power-up, when VDD reached VON and VIN reaches the VSH level, the SAVE output goes high, and the timer starts running, setting RES high after the time TTO (see Fig. 4). If VIN falls below VSL, the SAVE output goes low and stays low until VIN rises again above VSH. If VIN falls below the voltage VRL, the RES output will go low and the on-chip timer will stop. When VIN rises again above VSH, the timer will initiate a power-up sequence. The RES output may however be influenced independently of the voltage VIN by the timer action, see section "Combined Voltage and Timer Action". Monitoring the rough DC side of the regulator as shown in Fig. 12 is the only way to have advanced warning at power-down. Spikes on VIN should be filtered if they are likely to drop below VSL. The combination of VIN and VDD monitoring provide high system security: if VIN rises much faster than VDD, then the device starts the power-on sequence only when VDD reached VON (Fig. 3). Short circuits on the regulated supply voltage can be detected. Voltage Thresholds on VIN The H6006 is available with 3 different sets of thresholds:
SAVE RES
Note: The threshold levels are 9/8/7 V normally.These
are divided internally by 4 to give internal thresholds of 2.25 / 2 / 1.75 V. VDD = 5 V (thresholds Fig. 8 dependent on VDD). RVIN = ~ 100 k.
Version A2, B2: for monitoring of all unregulated voltage, where custom programming is required. Fixed resistor values can be used for programming.
H6006 A2, B2 H6006 A3, B3
VIN
VDD
VSS
SAVE RES
Note : the internal threshold levels are 2.25 / 2.00 / 1.75 V at VDD = 5 V (thresholds dependent on VDD) Fig. 9 RVIN = ~ 100 M.
Version A3, B3: for monitoring of regulated voltage, where no unregulated voltage is available (the tolerance is 10 %, see Table 4. For tighter tolerances, trimming can be used, see Fig. 10).
5 V 10%
VIN
VDD
SAVE RES
VSS
Note: the internal threshold levels are 2.00 / 1.95 / 1.90 V (thresholds dependent on the internal bandgap Fig. 10 reference) RVIN = ~ 100 M.
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H6006
Monitoring of the unregulated voltage require versions B1, A2 and B2. The versions are based on the principle that VDD rises with VIN on power-up and VDD holds up for a certain time after VIN starts dropping on power-down. The version B1 has a 100 k nominal resistance from VIN to VSS (internal voltage divider). The versions A2, B2, A3 and B3 have high impedance VIN inputs (see Fig. 7 and Table 4) for external threshold voltage programming by a voltage divider on pin VIN. The levels obtained are proportional to the internal levels VSH, VSL and VRL on the chip itself (see Electrical Specifications).
Timer Clearing and RES Action A negative edge or a negative pulse at the TCL input longer than 150 ns will reset the timer and set TO high. If a further TCL signal edge or pulse is applied before TTO timeout, TO will stay high and the timer will again be reset to zero (see Fig. 5). If no TCL signal is applied before the TTO timeout, TO will start to generate a square wave of period 2 x TTO starting with a low state. If no TCL signal is applied during the first low state of TO , then the RES output will go low and stay low until the next TCL signal, or until a fresh power-up sequence. Combined Voltage and Timer Action The combination of voltage and timer action is illustrated by the sequence of events shown in Fig. 6. One timeout period after VIN reached VSH, during power-up, RES goes inactive
high. No TCL pulse will have any effect until this power-on reset delay is completed. After completing the power-up sequence the watchdog timer starts acting. If no TCL pulse occurs, the timeout warning TO goes active low after one timeout period TTO. After each subsequent timeout period without a timer clear pulse TCL , TO changes its polarity providing a square wave signal. RES activates at the end of the first low state of the TO signal. A TCL pulse clears the watchdog timer and resets the TO and RES output inactive high again. A voltage drop below the VRL level overrides the timer and immediately forces RES and SAVE active low and disables TO . Any further TCL pulse has no effect until the next power-up sequence has complete
Timer Programming With pin RC unconnected, the on-chip RC oscillator together with its divider chain give a timeout TTO of typically 10 ms. For programming a different TTO, an approximation for calculating component values is given by the formula:
(32 + C1) * 1.6 =0.75 + * 1.024 V - 0.8 5.5 + DD R1
TTO
R1 min. = 10 k, C1 max. = 1 F If R1 is in M and C1 in pF, TTO will be in ms. Thus, a resistor decreases and a capacitor increases the interval to timeout. By using both external components, excellent temperature stability of TTO can be achieved. With TCL tied to either VDD or VSS, a precise square wave of period 2 x TTO is generated at the output TO . The oscillator and watchdog timer run so long as the chip is powered with at least the minimum positive supply voltage specified (VON), and so long as VIN remains above the level VRL after a power-up sequence. If the timer function is not required, input TCL should be tied to output TO to give a simple voltage monitor (see Fig. 14).
Typical Applications
>9 V
R1 = 470 k
Monitored Voltage
Voltage Regulator VIN VDD
5V
Adress Decoder SEL Latched Address Bus RD Microprocessor
H6006
TCL RC C1 = 220 pF RESET IR 1 IR 2 VSS
TO SAVE RES CS Disable RAM
TTO =~ 30 ms
Fig. 11
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H6006
Voltage Monitor with Spike Suppression
2.7 k Voltage Regulator VIN 330 nF VDD 5 VDC
10 VDC Rough
H6006
TCL
TO SAVE RES
VSS
Versions A1 or B1
Fig. 12
Watchdog and Power-On Reset
VDD Monitoring and Power-On Reset
H6006 A3, B3
TCL
TO
TCL
H6006 A3, B3
VIN
VDD
VIN
VDD TO SAVE RES
VSS
RES
VSS
If only VDD monitoring is used, (i.e.VIN and VDD common) then the version A3 or B3 with its constant thresholds are recommended. The power-on reset function is still available as the VDD monitoring is active.
Fig. 13
VIN monitoring and watchdog function not used. Versions A3 and B3 only.
Fig. 14
External Programming of RC Oscillator
R1 VDD VDD
R1 VDD TO
H6006
H6006
RC C1 VSS
RC RES VSS
RC2 RES C1 VSS
H6006
TCL
TO
TCL
TO
TCL
RES
C1 increases TTO
R1 shortens TTo
Note: using both external components R1 and C1 allows to achieve tighter timeout period tolerances.
This circuit provides independent programming of both timeout period and power-on reset delay.
Fig. 15
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H6006
Package Information
Dimensions of 8-Pin SOIC Package
D C
E 0 - 8 L H Dimensions in mm Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 Fig. 16
A1 B
A
e
4
3
2
5
6
7
8
Ordering Information
When ordering, please specify the complete Part Number
Part Number
H6006A2SO8A H6006A2SO8B H6006A3SO8A* H6006A3SO8B* H6006B1SO8A H6006B1SO8B* H6006B2SO8A H6006B2SO8B H6006B3SO8A H6006B3SO8B
Version
Threshol d (see Table 4)
2.00 1.95 8.00 2.00 1.95
Outpu t Type
Open drain
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Delivery Form
Stick Tape & Reel Stick Tape & Reel Stick Tape & Reel Stick Tape & Reel Stick Tape & Reel
A2 A3 B1 B2 B3
Pushpull
Package Marking (first line) 6006A2 6006A2 6006A3 6006A3 6006B1 6006B1 6006B2 6006B2 6006B3 6006B3
Temperature Range
-40 to +85 C
* = non stock item. Might be available on request and upon minimum order quantity (please contact EM Microelectronic).
Note: Other versions are no longer available
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) EM Microelectronic-Marin SA, 07/04, Rev. G
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